km23v32005b(e)ty/km23s32005b(e)ty cmos mask rom preliminary 32m-bit (4mx8 /2mx16) cmos mask rom the km23v32005b(e)ty and km23s32005b(e)ty are fully static mask programmable rom fabricated using silicon gate cmos process technology, and is organized either as 4,194,304 x8 bit(byte mode) or as 2,097,152x16 bit(word mode) depending on bhe voltage level.(see mode selection table) this device includes page read mode function, page read mode allows four to eight words of data to read fast in the same page, ce and a 3 ~ a 20 should not be changed. this device operates with low power supply, and all inputs and outputs are ttl compatible. because of its asynchronous operation, it requires no external clock assuring extremely easy operation. it is suitable for use in program memory of microprocessor, and data memory, character generator. the km23v32005b(e)ty and km23s32005b(e)ty are pack- aged in a 48-tsop1. general description features switchable organization 4,194,304x8(byte mode) 2,097,152x16(word mode) fast access time random access time/page access time 3.3v operation : 80/30ns(max.) 3.0v operation : 100/30ns(max.) 2.5v operation : 120/50ns(max.) supply voltage km23v32005b(e)ty : 2.7v ~ 3.6v km23s32005b(e)ty : 2.3v ~ 2.7v current consumption operating : 60ma(max.) standby : 30 m a(max.) fully static operation all inputs and outputs ttl compatible three state outputs package -. km23v(s)32005b(e)ty : 48-tsop1-1218 a 20 x a 0~ a 2 and decoder buffers a 3 y and decoder buffers memory cell sense amp. control logic matrix (2,097,152x16/ 4,194,304x8) data out buffers a -1 ce oe bhe . . . . . . . . q 0 /q 8 q 7 /q 15 . . . functional block diagram pin name pin function a 0 - a 2 page address inputs a 3 - a 20 address inputs q 0 - q 14 data outputs q 15 /a -1 output 15(word mode)/ lsb address(byte mode) bhe word/byte selection ce chip enable oe output enable v cc power v ss ground n.c no connection
km23v32005b(e)ty/km23s32005b(e)ty cmos mask rom preliminary bhe a 16 a 15 a 14 a 13 a 12 a 11 a 9 a 8 a 10 v ss a 20 a 18 a 17 a 7 a 6 a 5 a 4 km23v32005b(e)ty km23s32005b(e)ty 1 2 48 47 3 4 5 6 7 8 9 10 39 11 12 37 13 14 15 16 17 18 19 20 21 22 tsop a 3 a 1 q 4 pin configuration 23 24 a 0 ce v ss oe q 0 q 8 q 1 q 3 q 9 q 2 q 10 46 45 44 43 42 41 40 38 36 35 34 33 32 31 30 29 28 27 26 25 q 15/ a 1 q 7 q 14 q 6 q 13 q 5 q 12 q 11 v ss a 2 a 19 v ss v ss v ss v ss v cc v cc v ss v ss productminformation product operating temp range v cc range speed(ns) taa/tpa KM23V32005BTY 0 c ~ 70 c 3.3v/3.0v 80(30)/100(30) km23s32005bty 2.5v 120(50) km23v32005bety -20 c ~ 85 c 3.3v/3.0v 80(30)/100(30) km23s32005bety 2.5v 120(50) absolute maximum ratings note : permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating con - ditions for extended periods may affect device reliability. item symbol rating unit remark voltage on any pin relative to v ss v in -0.3 to+4.5 v - temperature under bias t bias -55 to+150 c - storage temperature t stg -55 to+150 c - operating temperature t a 0 to+70 c KM23V32005BTY km23s32005bty -20 to+85 c km23v32005bety km23s32005bety 32m-bit (4mx8 /2mx16) cmos mask rom
km23v32005b(e)ty/km23s32005b(e)ty cmos mask rom preliminary recommended operating conditions (voltage reference to v ss ) item symbol min typ max unit supply voltage v cc 2.7/3.0 3.0/3.3 3.3/3.6 v 2.3 2.5 2.7 v supply voltage v ss 0 0 0 v mode selection ce oe bhe q 15 /a -1 mode data power h x x x standby high-z standby l h x x operating high-z active l l h output operating q 0 ~q 15 : dout active l input operating q 0 ~q 7 : dout q 8 ~q 14 : hi-z active capacitance ( t a =25 c, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test conditions min max unit output capacitance c out v out =0v - 12 pf input capacitance c in v in =0v - 12 pf dc characteristics note : minimum dc voltage(v il ) is -0.3v an input pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input pins(v ih ) is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. parameter symbol test conditions min max unit operating current i cc ce = oe =v il all outputs open v cc =3.3v 0.3v - 60 ma v cc =3.0v 0.3v - 50 ma v cc =2.5v 0.2v - 40 ma standby current(ttl) i sb1 km23v32005b(e)ty ce =v ih , all outputs open - 500 m a km23s32005b(e)ty - 100 m a standby current(cmos) i sb2 km23v32005b(e)ty ce =v cc , all outputs open - 30 m a km23s32005b(e)ty - 5 m a input leakage current i li v in =0 to v cc - 10 m a output leakage current i lo v out =0 to v cc - 10 m a input high voltage, all inputs v ih 2.0 v cc +0.3 v input low voltage, all inputs v il km23v32005b(e)ty -0.3 0.6 v km23s32005b(e)ty -0.3 0.4 v output high voltage level v oh km23v32005b(e)ty i oh =-400 m a 2.4 - v km23s32005b(e)ty i oh =-400 m a 2.0 - v output low voltage level v ol i ol =2.1ma - 0.4 v
km23v32005b(e)ty/km23s32005b(e)ty cmos mask rom preliminary test conditions item value input pulse levels 0.45v to 2.4v(at v cc =3.3v/3.0v) 0.4v to 2.2v (at v cc =2.5v) input rise and fall times 10ns input and output timing levels 1.5v (at v cc =3.3v/3.0v) 1.1v (at v cc =2.5v) output loads 1 ttl gate and c l =100pf ac characteristics (v cc =3.3v/3.0v 0 .3v, v cc =2.5v 0.2v, unless otherwise noted.) read cycle item symbol v cc =3.3v 0.3v v cc =3.0v 0.3v v cc =2.5v 0.2v unit min max min max min max read cycle time t rc 80 100 120 ns chip enable access time t ace 80 100 120 ns address access time t aa 80 100 120 ns page access time t pa 30 30 50 ns output enable access time t oe 30 30 50 ns output or chip disable to output high-z t df 20 20 20 ns output hold from address change t oh 0 0 0 ns
km23v32005b(e)ty/km23s32005b(e)ty cmos mask rom preliminary timing diagram read add ce oe d out a 0 ~a 20 a -1(*1) d 0 ~d 7 d 8 ~d 15(*2) page read oe add d out ce add a 0 ,a 1, a 2 add1 add2 valid data valid data t oh t df(*3) valid data valid data valid data valid data 1st 2nd 3rd a 3 ~a 20 t df(*3) ? ? ? ? ? ? t rc t ace t oe t aa notes : *1. byte mode only. a -1 is least significant bit address.(bhe = v il ) *2. word mode only.(bhe = v ih ) *3. t df is defined as the time at which the outputs achieve the open circuit condition and is not referenced to v oh or v ol level. t pa t aa
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